Anritsu MP2110A BERTWave - Page 81

2.2 Part Names
2-7
2
Before Use
BERT Panel
Figure 2.2.1-3 BERT Panel Names (MP2110A-014)
The following tables describe the panel.
Table 2.2.1-2 Lamp List
Name Description
Output
Lit green during signal output from PPG connector.
Error
Lit orange at following condition at ED:
- Unable to synchronize pattern (Sync Loss).
- Bit error detected.
Status
Lit green during normal operation while able to receive remote
commands.
Fail
Lit red when hardware fault detected.
This may light briefly at power-on, but there is no abnormality.
Table 2.2.1-3 Connector List
Connector Name Description Level Range
Clk Out
Outputs divided clock.
0.3 to 0.5 Vp-p
Ext Clk In
For input of external clock.
0.2 to 1.6 Vp-p
Sync Out
Outputs the clock synchronized to
PPG pattern.
V
OH
: –0.2 to 0.05 V
Sync
Out
Outputs the inverted clock
synchronized to PPG pattern.
V
OL
: –1.2 to –0.7 V
Data Out
Outputs the PPG data.
0.1 to 0.8 Vp-p
Data
Out
Outputs the PPG inverted data.
(Variable)*
Data In
ED data input.
0.05 to 0.8 Vp-p*
Data
In
ED inverted data input.
*: Same for Ch1 to Ch4.
Clk Out
Channel 3
Connectors
Clk Out
Channel 1
Connectors
BERT
Output 1 2 3 4
Fail
Ext Clk In
1.6Vp-p Max
Sync Out
Sync Out
Data In
Data Out
Data Out
Data In
PPG
ED
1Vp-p Max
Ch 3
Data In
Data Out
Data Out
Data In
PPG
ED
1Vp-p Max
Ch 4
Data In
Data Out
Data Out
Data In
PPG
ED
1Vp-p Max
Ch 2
Data In
Data Out
Data Out
Data In
PPG
ED
1Vp-p Max
Ch 1
Error 1 2 3 4
Status Fail
Channel 4
Connectors
Channel 2
Connectors
Status
Ext Clk In
Error
Output
Sync Out
Sync Out