4 Fault Isolation
4.9 HPMM Alphanumeric Display
368 HPM High-Performance Process Manager Service R688
Honeywell December 2020
HPMM RAM Retention Startup Sequence
An HPMM RAM Retention startup is performed whenever power is restored and the CMOS memory
battery backup was successful in maintaining the integrity of the operating personality software and
database in the RAM memory.
When an HPMM RAM Retention Startup process is performed, only the Communications processor is
initially released from reset and executes from the Startup and Base Utility firmware. Once a RAM
Retention Startup is considered possible, program execute control is transferred to the previously loaded
Communications processor software image. The Control processor and I/O Link processors are then
released so that they can verify their respective Startup conditions. The following table lists a HPMM
RAM Retention startup to Run state.
ATTENTION
Due to security authentication in the EUCN network, at least one ENIM must
be up and running in order for an EHPM node to be able to perform a RAM
Retention startup. The EHPM is re-authenticated during a RAM retention
restart, and the ENIM is the master authenticator node.
ATTENTION
Due to the processor restart time of the EHPM, the RAM Retention response
time for the EHPM is slightly longer than that of a HPM.
Table 74 RAM Retention Startup Display Sequence
In the Run state (UCN node 39). This display does
not blink.
Communications processor based tests
Global DRAM initialization
Communications processor Local RAM destructive
pattern test
Communications processor Local RAM
initialization
UCN TBC Private RAM destructive pattern test
UCN TBC Private RAM initialization
Communications processor builds memory
reference table.
Transition to the SW Alive state.
Monitor Control processor local state change (i.e
release Control processor from reset state)
Control processor Local RAM destructive pattern
test
Control processor Local RAM initialization
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