Intel Pentium 4 User Manual

Layout Review Checklist
R
270 Intel
®
Pentium
®
4 Processor / Intel
®
850 Chipset Family Platform Design Guide
√ Recommendations Reason/Impact/Documentation
• Address signal (A[35:3]# and REQ[4:0]#)
length should be 2 inches – 10 inches pin-
to-pin. Address signals of the same source
synchronous group should be routed to the
same pad-to-pad length ±200 mils. Length
must be added to the motherboard to
compensate for package length differences.
• The length compensation will result in
minimizing the source synchronous skew
that exists on the system bus. Without trace
matching and length compensation flight
times between the data signals and the
strobes will result in inequity between the
setup and hold times.
• Refer to Chapter 2.
• ADSTB[1:0]# length should be 2 inches –
10 inches pin-to-pin. Address signals of the
same source synchronous group should be
routed to the same pad-to-pad length
±200 mils. Length must be added to the
motherboard to compensate for package
length differences.
• The impact of this routing recommendation
causes the strobe to be received closer to
the center of the data pulse, which results in
reasonably comparable setup and hold
times.
• Refer to Chapter 2.
All common clock AGTL+ signals (See below)
routed 6 inches – 10 inches (pin-to-pin). No
length compensation is necessary.
BPRI# DEFER# RESET#
RS[2:0]# RSP# TRDY#
AP[1:0]# ADS# BINIT#
BNR# BPM[5:0]# BR0#
DBSY# DP[3:0]# DRDY#
HIT# HITM# LOCK#
MCERR#
• Refer to Chapter 2.
• All signals impedance’s should equal
50
Ω ±15%
• Refer to Chapter 2.

Intel Pentium 4 Specifications

General

Architecture	x86
Core Count	1
Microarchitecture	NetBurst
Manufacturer	Intel
Core Names	Willamette, Northwood, Prescott, Cedar Mill
Virtualization Technology	No
Release Date	November 20, 2000
Clock Speed	1.3 GHz to 3.8 GHz
FSB Speed	400 MHz to 1066 MHz
Socket	Socket 423, Socket 478, LGA 775
Introduced	2000
Product Line	Pentium
Front Side Bus	400 MHz to 1066 MHz
Hyper-Threading	Yes (Prescott and later)
64-bit Support	Yes (Prescott and later)
Instruction Set	MMX, SSE, SSE2, SSE3
Discontinued	2008
Process Technology	180 nm, 130 nm, 90 nm, 65 nm
L2 Cache	256 KB, 512 KB, 1 MB, 2 MB
Lithography	180 nm, 130 nm, 90 nm, 65 nm
L1 Cache	8 KB