Keysight B2961A/B2962A SCPI Command Reference, Edition 6 3- 13
Common Commands
*SRE
*SRE
This command sets the value of the Service Request Enable register. This register
determines which bits from the Status Byte register are summed to set the Master
Status Summary (MSS) bit and the Request for Service (RQS) summary bit. A 1 in
the bit position enables the corresponding event. For the SCPI status system, see
“Status System Diagram” on page 1-17.
The query reads the enable register and returns a decimal value which corresponds
to the binary-weighted sum of all bits set in the register.
Syntax *SRE value
*SRE?
Parameter value Decimal value which corresponds to the binary-weighted sum of
the bits in the register (see
Table 3-3). Parameter data type is NRf.
For example, to enable bit 0 (decimal value = 1), bit 3 (decimal value = 8), and bit 6
(decimal value = 64), the corresponding decimal value would be 73 (1 + 8 + 64).
Query response value <newline><^END>
value is the binary-weighted sum of all bits set in the register. For example, if bit 3
(decimal value = 8) and bit 7 (decimal value = 128) are enabled, the query command
will return 136. Response data type is NR1.
Remarks Bit definitions of the Status Byte register are shown in Table 3-3.
All of the enabled events of the Standard Event Status Enable register are logically
ORed to cause the Event Summary Bit (ESB) of the Status Byte register to be set.
All such enabled bits are then logically ORed to cause the MSS bit (bit 6) of the
Status Byte register to be set.
When the controller conducts a serial poll in response to SRQ, the RQS bit is
cleared, but the MSS bit is not. When *SRE is cleared (by programming it with 0),
the power system cannot generate an SRQ to the controller.
The *CLS (clear status) command will not clear the enable register but it does clear
all bits in the event register.
A :STATus:PRESet command does not clear the bits in the Status Byte register.
To Next Page
Loading...
Need help?
General
