Issue 5 November 2000
363-206-208
Introduction
Lucent Technologies - Proprietary
See Notice on first page
DDM-2000 OC-12 Releases
The DDM-2000 OC-12 Multiplexer features will be released in distinct phases. This
manual covers installation of Release 3 (STS-1 Path-Switched Ring), Release 5 (New
controllers providing data communication channel (DCC) connectivity interworking with
FT-2000), and Release 7 (Interoperability with multivendor SONET networks)
applications for the OC-12 Multiplexer. This manual will be updated to cover additional
releases as they become available.
DDM-2000 OC-12 Multiplexer Shelf
Description
The DDM-2000 OC-12 shelf is divided into several distinct areas. The following areas
are described, beginning at the right of the shelf working toward the left side.
On the right side of the shelf is the user panel. Each shelf is equipped with a user panel
which provides system level information and control functions. The user panel is also
equipped with the shelf’s -48 V fuses, EIA-232D port for connection with a craft
interface terminal (CIT), and electrostatic discharge (ESD) grounding jack.
Located next to the user panel is the required OHCTL circuit pack. The OHCTL
provides order wire capabilities, parallel elemetry indications, and miscellaneous
discrete outputs. In addition, the OHCTL provides DCC between the DDM-2000 OC-12
shelves for single-ended operation (SEO).
NOTE:
Parallel telemetry is not available in OC-12, Release 7.
Located to the left of the OHCTL is the required system controller (SYSCTL) circuit
pack. The SYSCTL serves as the main controller for the system and oversees
operations of the DDM-2000 OC-12 Multiplexer (switching, performance monitoring,
etc.). Located on the SYSCTL is a 7-segment display and far-end select (FE SEL) and
update/initialize (UPD/INIT) pushbuttons. These controls and displays are used for
single-ended operation (SEO) and executing installation self tests.
Located to the left of the SYSCTL are the FUNCTION UNITS (FN) low speed
transmission circuit packs. There are four pairs of FN packs with each pair responsible
for the bidirectional transport of three DS3 low speed input signals when BBG12B 3DS3
circuit packs are used, three EC-1 ow speed input signals when the BBG11 3STS-1E
circuit packs are used, or one OC-3 input signal where 21G-U or 21D-U optical line
interface units (OLIUs) are used. Each FN pair consists of a working and standby circuit
pack which provides 1x1 low speed protection. The 3DS3 or 3STS-1E circuit packs
receive three DS3 or EC-1 signals respectively, and maps them into three distinct STS-
1 signals which are sent to the time slot interchange (TSI) circuit packs. The FN OLIU
circuit packs receive an OC-3 signal and map it into three distinct STS-1 signals which
are sent to the TSI circuit packs.
Located to the left of the FN circuit packs are two TSI circuit packs. The TSI circuit
packs act as a bidirectional interface for the STS-1 signals between the MAIN OLIU
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