SM 179 D163
6805E4
Bit 0 – OHS (on hook speed)
0: OHS=0
1: OHS=1
Bit 1 – SQ (spark quench)
0: SQ=00
1: SQ=11
Bit 2 – RZ (call signal Impedance)
0: RZ=0 (high)
1: RZ=1 (low)
Bit 3 – RT (call signal detection level)
0: RT=0 (low)
1: RT=1 (high)
Bit 4 – ILIM (DC limitation)
0: ILIM=0 (CTR 21)
1: ILIM=1 (other than CTR 21)
Bit 5 –FILTER
0: FILTER=0 (around 5Hz)
1: FILTER=1 (around 200Hz)
Bits 6 to 7 – Calibration in off hook state
Bit 6:0, Bit 7: 0 = off hook to ACAL:128 ms, off hook to MCAL: 1000 ms
Bit 6:1, Bit 7: 0 = off hook to ACAL:128 ms, off hook to MCAL: 500 ms
Bit 6:0, Bit 7: 1 = off hook to ACAL:128 ms (no MCAL)
Bit 6:1, Bit 7: 1 = off hook to ACAL:8 ms (no MCAL)
6805E5
Bits 0 to 6 – Not used
Bits 7 – Energy saving for DSP, COMBLK, SiDAA
0: Does not save energy
1: Saves energy
NOTES
1. If a setting is not required, store FF in the address.
2. Italy and Belgium only
RAM address 68055E: the lower four bits have the following meaning.
Bit 2 - 1: International dial tone cadence detection enabled (Belgium)
Bit 1 - Not used
Bit 0 - 1: PSTN dial tone cadence detection enabled (Italy)
If bit 0 or bit 2 is set to 1, the functions of the following RAM addresses are changed.
680508 (if bit 0 = 1) or 680538 (if bit 2 = 1): tolerance for on or off state
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