Sel SEL-787 - Settings for Synchrophasors; Table H.1 PMU Settings in the SEL-787 for C37.118 Protocol in Global Settings

H.4
SEL-787 Relay Instruction Manual Date Code 20150130
Synchrophasors
Settings for Synchrophasors
Settings for Synchrophasors
The phasor measurement unit (PMU) settings are listed in Table H.1. Modify
these settings when you want to use the C37.118 synchrophasor protocol.
The Global enable setting EPMU must be set to Y before the remaining
SEL-787 synchrophasor settings are available. No synchrophasor data
collection can take place when EPMU := N.
You must make the serial port settings in Table H.2 to transmit data with a
synchrophasor protocol. It is possible to set EPMU := Y without using any
serial ports for synchrophasor protocols. For example, the serial port
MET PM ASCII command can still be used.
Certain settings in Table H.1 are hidden, depending on the status of other
settings. For example, if PHDATAI := NA, the PHCURR setting is hidden to
limit the number of settings for your synchrophasor application.
The Port settings for PROTO := PMU, shown in Table H.2, do not include the
settings DATABIT and PARITY; these two settings are internally fixed as
Table H.1 PMU Settings in the SEL-787 for C37.118 Protocol in Global
Settings
Setting Description Default
EPMU Enable Synchronized Phasor Measurement
(Y, N)
N
a
a
Set EPMU := Y to access the remaining settings.
MRATE Messages per Second {1, 2, 5, 10} 10
PMSTN Station Name (16 characters) SEL-787 XFRMR 1
PMID PMU Hardware ID (1–65534) 1
PHDATAV Phasor Data Set, Voltages (V1, ALL, NA) V1
VCOMP Voltage Angle Comp Factor
(–179.99 to 180 deg)
0.00
PHDATAI Phasor Data Set, Currents (I1, ALL, NA) NA
PHCURR
b
b
Setting hidden when PHDATAI := NA.
Current Source (IW1, IW2, BOTH) BOTH
IW1COMP IW1 Angle Comp Factor
(–179.99 to 180 deg)
0.00
IW2COMP IW2 Angle Comp Factor
(–179.99 to 180 deg)
0.00
NUMANA Number of Analog Values (0–4) 0
NUMDSW Number of 16-bit Digital Status Words (0, 1) 0
TREA1 Trigger Reason Bit 1 (SEL
OGIC)TRIP or ER
TREA2 Trigger Reason Bit 2 (SEL
OGIC) 81D1T OR 81D2T OR
81D3T OR 81D4T
TREA3 Trigger Reason Bit 3 (SEL
OGIC) 59P1T OR 59P2T OR
59Q1T OR 59Q2T
TREA4 Trigger Reason Bit 4 (SEL
OGIC) 27P1T OR 27P2T
PMTRIG Trigger (SEL
OGIC) TREA1 OR TREA2
OR TREA3 OR
TREA4
IRIGC IRIG-B Control Bits Definition (NONE,
C37.118)
NONE