Sel SEL-787 - Page 583

J.9
Date Code 20150130 Instruction Manual SEL-787 Relay
Relay Word Bits
Definitions
CF2 Breaker 2 Close condition failure on 32
CFGFLT Asserts on failed settings interdependency check during Modbus setting change 26
CL1 Close SEL
OGIC control equation CL1 35
CL2 Close SEL
OGIC control equation CL2 35
CLOSE1 Close logic output for Breaker1 32
CLOSE2 Close logic output for Breaker2 32
COMMFLT Time-out of internal communication between CPU board and DeviceNet board 26
COMMIDLE DeviceNet card in programming mode 26
COMMLOSS DeviceNet communication failure 26
DI_xn Distortion index, where x = phase A, B, or C and n = winding 1 or 2 104
DNAUXn DeviceNet/ModBus AUXn assert bit, where n = 1 through 8 36
DNAUXn DeviceNet/ModBus AUXn assert bit, where n = 9 through 11 37
DSABLSET SEL
OGIC control equation: Do not allow settings changes from front-panel interface when
asserted
28
DST Daylight-Saving Time 105
DSTP Daylight-Saving Time Pending 105
ER Event report trigger SEL
OGIC control equation 27
FAULT Indicates fault condition. Asserts when SEL
OGIC control equation FAULT result in a logical 1. 25
FREQTRK Frequency tracking enable bit-tracking enabled when bit is asserted 27
GNDEM Zero sequence current demand pickup 41
HALARM Diagnostics failure 28
IN301–IN304 Contact inputs IN301–IN304 (available only with optional I/O module 22
IN305–IN308 Contact inputs IN305–IN308 (available only with optional I/O module 22
IN401–IN404 Contact inputs IN401–IN404 (available only with optional I/O module 23
IN405–IN408 Contact inputs IN405–IN408 (available only with optional I/O module 23
IN501–IN504 Contact inputs IN501–IN504 (available only with optional I/O module 24
IN505–IN508 Contact inputs IN505–IN508 (available only with optional I/O module 24
INnnn Contact inputs IN101 and IN102 21
INR1 87-1 Differential element in high security mode (see Figure 4.4)37
INR2 87-2 Differential element in high security mode (see Figure 4.4)37
INR3 87-3 Differential element in high security mode (see Figure 4.4)37
IRIGOK IRIG-B time synch input data are valid 25
LB01–LB08 Local Bits 01 through 08 42
LB09–LB16 Local Bits 09 through 16 43
LB17–LB24 Local Bits 17 through 24 44
LB25–LB32 Local Bits 25 through 32 45
LBOKA Channel A, looped back ok 74
LBOKB Channel B, looped back ok Channel B, channel unavailability over threshold 74
LINKA Assert if Ethernet Port A detects link 25
Table J.2 Relay Word Bit Definitions for the SEL-787 (Sheet 6 of 10)
Bit Definition Row