ST STM32WL55JC

Contents RM0453
10/1454 RM0453 Rev 2
7.4.4 RCC PLL configuration register (RCC_PLLCFGR) . . . . . . . . . . . . . . . 304
7.4.5 RCC clock interrupt enable register (RCC_CIER) . . . . . . . . . . . . . . . . 307
7.4.6 RCC clock interrupt flag register (RCC_CIFR) . . . . . . . . . . . . . . . . . . 308
7.4.7 RCC clock interrupt clear register (RCC_CICR) . . . . . . . . . . . . . . . . . 309
7.4.8 RCC AHB1 peripheral reset register (RCC_AHB1RSTR) . . . . . . . . . . 311
7.4.9 RCC AHB2 peripheral reset register (RCC_AHB2RSTR) . . . . . . . . . . 311
7.4.10 RCC AHB3 peripheral reset register (RCC_AHB3RSTR) . . . . . . . . . . 312
7.4.11 RCC APB1 peripheral reset register 1 (RCC_APB1RSTR1) . . . . . . . . 313
7.4.12 RCC APB1 peripheral reset register 2 (RCC_APB1RSTR2) . . . . . . . . 314
7.4.13 RCC APB2 peripheral reset register (RCC_APB2RSTR) . . . . . . . . . . 315
7.4.14 RCC APB3 peripheral reset register (RCC_APB3RSTR) . . . . . . . . . . 316
7.4.15 RCC AHB1 peripheral clock enable register (RCC_AHB1ENR) . . . . . 317
7.4.16 RCC AHB2 peripheral clock enable register (RCC_AHB2ENR) . . . . . 318
7.4.17 RCC AHB3 peripheral clock enable register (RCC_AHB3ENR) . . . . . 319
7.4.18 RCC APB1 peripheral clock enable register 1 (RCC_APB1ENR1) . . . 320
7.4.19 RCC APB1 peripheral clock enable register 2 (RCC_APB1ENR2) . . . 321
7.4.20 RCC APB2 peripheral clock enable register (RCC_APB2ENR) . . . . . 322
7.4.21 RCC APB3 peripheral clock enable register (RCC_APB3ENR) . . . . . 323
7.4.22 RCC AHB1 peripheral clock enable in Sleep mode register
(RCC_AHB1SMENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
7.4.23 RCC AHB2 peripheral clock enable in Sleep mode register
(RCC_AHB2SMENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
7.4.24 RCC AHB3 peripheral clock enable in Sleep and Stop mode register
(RCC_AHB3SMENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
7.4.25 RCC APB1 peripheral clock enable in Sleep mode register 1
(RCC_APB1SMENR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
7.4.26 RCC APB1 peripheral clock enable in Sleep mode register 2
(RCC_APB1SMENR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
7.4.27 RCC APB2 peripheral clock enable in Sleep mode register
(RCC_APB2SMENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
7.4.28 RCC APB3 peripheral clock enable in Sleep mode register
(RCC_APB3SMENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
7.4.29 RCC peripherals independent clock configuration register
(RCC_CCIPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
7.4.30 RCC Backup domain control register (RCC_BDCR) . . . . . . . . . . . . . . 334
7.4.31 RCC control/status register (RCC_CSR) . . . . . . . . . . . . . . . . . . . . . . . 336
7.4.32 RCC extended clock recovery register (RCC_EXTCFGR) . . . . . . . . . 339
7.4.33 RCC CPU2 AHB1 peripheral clock enable register
(RCC_C2AHB1ENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341