77
No
Yes
NMI?
No
Yes
User break?
No
Yes
Level 15
interrupt?
No
Yes
I3 to I0 ≤
level 14?
No
Yes
Level 14
interrupt?
No
Yes
Yes
I3 to I0 ≤
level 13?
No
Yes
Level 1
interrupt?
No
Yes
I3 to I0 =
level 0?
No
Program
execution state
IRQOUT low
*1
Push SR onto stack
Push PC onto stack
IRQOUT high
*2
Interrupt?
Copy level of accep-
tance from I3 to I0
Read exception
vector table
Branch to exception
handling routine
I3 to I0: Interrupt mask bits of status register
Notes: *1 IRQOUT is the same signal as the interrupt request signal to the CPU (figure 5.1). The
IRQOUT pin returns to the high level when the interrupt controller has accepted the
interrupt of a level higher than that specified by bits I3 to I0 in the CPU’s status
register.
*2 If the accepted interrupt is edge-sensed, the IRQOUT pin returns to the high level
when the instruction to be executed by the CPU is replaced by interrupt exception
handling (before the status register is saved to the stack ). If the interrupt controller has
accepted another interrupt of a level higher than the current interrupt, and has sent an
interrupt request to the CPU, however, the IRQOUT pin remains low.
Figure 5.2 Flowchart of Interrupt Operation
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