Hitachi SH7032 - 10.6.11 Note on Writing in Synchronizing Mode; 10.6.12 Note on Setting Reset-Synchronized PWM Mode;Complementary PWM Mode

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10.6.11 Note on Writing in Synchronizing Mode
After synchronizing mode is selected, if TCNT is written by byte access, all 16 bits of all
synchronized counters assume the same value as the counter that was addressed.
Example: Figures 10.67 and 10.68 show byte write and word write when channels 2 and 3 are
synchronized
AXTCNT2
AXTCNT3
YATCNT2
YATCNT3
Write A to lower
byte of channel 3
Write A to upper
byte of channel 2
WXTCNT2
YZTCNT3
Upper
byte
Lower
byte
Upper
byte
Lower
byte
Upper
byte
Lower
byte
Figure 10.67 Byte Write to Channel 2 or Byte Write to Channel 3
ABTCNT2
ABTCNT3
Word write of AB
for channel 2 or 3
WXTCNT2
YZTCNT3
Upper
byte
Lower
byte
Upper
byte
Lower
byte
Figure 10.68 Word Write to Channel 2 or Word Write to Channel 3
10.6.12 Note on Setting Reset-Synchronized PWM Mode/Complementary PWM Mode
When the CMD1 and CMD0 bits in TFCR are set, note the following.
1. Writes to CMD1 and CMD0 should be carried out while TCNT3 and TCNT4 are halted.
2. Changes of setting from reset-synchronized PWM mode to complementary PWM mode and
vice versa are prohibited. Set reset-synchronized PWM mode or complementary PWM mode
after first setting normal operation (clear CMD1 bit to 0).