Hitachi SH7032 - ITU Register Descriptions; Timer Start Register (TSTR)

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Table 10.3 Register Configuration (cont)
Channel Name
Abbrevi-
ation R/W
Initial
Value Address
*
1
Access
Size
4 (cont) Timer counter 4 TCNT4 R/W H'00 H'5FFFF36 8, 16
H'5FFFF37 8, 16
General register A4 GRA4 R/W H'FF H'5FFFF38 8, 16, 32
H'5FFFF39 8, 16, 32
General register B4 GRB4 R/W H'FF H'5FFFF3A 8, 16, 32
H'5FFFF3B 8, 16, 32
Buffer register A4 BRA4 R/W H'FF H'5FFFF3C 8, 16, 32
H'5FFFF3D 8, 16, 32
Buffer register B4 BRB4 R/W H'FF H'5FFFF3E 8, 16, 32
H'5FFFF3F 8, 16, 32
Notes: *1 Only the values of bits A27–A24 and A8–A0 are valid; bits A23–A9 are ignored. For
details on the register addresses, see section 8.3.5, Area Descriptions.
*2 Only 0 can be written to clear flags.
10.2 ITU Register Descriptions
10.2.1 Timer Start Register (TSTR)
The timer start register (TSTR) is an eight-bit read/write register that starts and stops the timer
counters (TCNT) of channels 0–4. TSTR is initialized to H'E0 or H'60 by a reset and in standby
mode.
Bit: 7 6 5 4 3 2 1 0
Bit name: — — — STR4 STR3 STR2 STR1 STR0
Initial value: * 1100000
R/W: — — — R/W R/W R/W R/W R/W
Note: *Undefined