298
10.6.10 Contention between BR Write and Input Capture
When a buffer register (BR) is being used as an input capture register and an input capture signal
is generated in the T3 state of the write cycle, the buffer operation takes priority over the BR write.
The timing is shown in figure 10.66.
T1T2 T3
BR write cycle
BR address
NX
CK
Address
Internal
write signal
Input capture
signal
GR
BR
MN
TCNT value
Figure 10.66 Contention between BR Write and Input Capture
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