Hitachi SH7032 - Refresh Timer Control;Status Register (RTCSR) BSC

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A.2.47 Refresh Timer Control/Status Register (RTCSR) BSC
• Start Address: H'5FFFFAE
• Bus Width: 8/16/32 (read), 16 (write)
Register Overview:
Bit: 15 14 13 12 11 10 9 8
Bit name: — — — — — — — —
Initial value: 0 0 0 0 0 0 0 0
R/W: — — — — — — — —
Bit: 7 6 5 4 3 2 1 0
Bit name: CMF CMIE CKS2 CKS1 CKS0 — — —
Initial value: 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W — — —
Table A.48 RSTCR Bit Functions
Bit Bit Name Value Description
7 Compare match flag (CMF) 0 RTCNT and RTCOR values do not match(Initial value)
Clear Condition: CMF read, then 0 written in CMF
1 RTCNT and RTCOR values match
6 Compare match interrupt 0 Compare match interrupt (CMI) disabled (Initial value)
enable (CMIE)
1 Compare match interrupt (CMI) enabled
5–3 Clock select 2–0 (CKS2– 0 0 0 Clock input disabled (Initial value)
CKS0)
001φ/2
010φ/8
011φ/32
100φ/128
101φ/512
110φ/2048
111φ/4096