Hitachi SH7032 - Break Bus Cycle Register (BBR) UBC

605
A.2.39 Break Bus Cycle Register (BBR) UBC
• Start Address: H'5FFFF98
• Bus Width: 8/16/32
Register Overview:
Bit: 15 14 13 12 11 10 9 8
Bit name: — — — — — — — —
Initial value: 0 0 0 0 0 0 0 0
R/W: — — — — — — — —
Bit: 7 6 5 4 3 2 1 0
Bit name: CD1 CD0 ID1 ID0 RW1 RW0 SZ1 SZ0
Initial value: 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Table A.40 BBR Bit Functions
Bit Bit name Value Description
7,6 CPU cycle/DMA cycle 0 0 User break interrupt not generated (Initial value)
select (CD1, CD0)
0 1 CPU cycle is break condition
1 0 DMA cycle is break condition
1 1 CPU cycle and DMA cycle are both break conditions
5,4 0 0 User break interrupt not generated (Initial value)
0 1 Instruction fetch cycle is break condition
1 0 Data access cycle is break condition
1 1 Instruction fetch cycle and data access cycle are both
break conditions
3,2 Read/write select 0 0 User break interrupt not generated (Initial value)
(RW1, RW0)
0 1 Read cycle is break condition
1 0 Write cycle is break condition
1 1 Read cycle and write cycle are both break conditions
1,0 Operand size select
(SZ1, SZ0)
0 0 Operand size not included in the break conditions
(Initial value)
0 1 Byte access is break condition
1 0 Word access is break condition
1 1 Longword access is break condition
Instruction fetch/data
access select
(ID1, ID0)