579
A.2.15 Timer I/O Control Registers 0–4 (TIOR0–TIOR4) ITU
• Start Address: H'5FFFF05 (channel 0), H'5FFFF0F (channel 1), H'5FFFF19 (channel 2),
H'5FFFF23 (channel 3), H'5FFFF33 (channel 4)
• Bus Width: 8
Register Overview:
Bit: 7 6 5 4 3 2 1 0
Bit name: — IOB2 IOB1 IOB0 — IOA2 IOA1 IOA0
Initial value: * 0001000
R/W: — R/W R/W R/W — R/W R/W R/W
Note: *Undetermined
Table A.16 TIO0–TIO4 Bit Functions
Bit Bit name Value Description
6–4 I/O control B2–0
(IOB2–IOB0)
0 0 0 GRB is output
compare register
Pin output due to compare match
disabled (Initial value)
0 0 1 0 output on GRB compare match
0 1 0 1 output on GRB compare match
0 1 1 Toggle output on GRB compare match
(1 output on channel 2 only)
1 0 0 GRB is input Input capture to GRB on rising edge
101
capture register
Input capture to GRB on falling edge
11* Input capture on both rising and falling
edges
2–0 I/O control A2–0
(IOA2–IOA0)
0 0 0 GRA is output
compare register
Pin output due to compare match
disabled (Initial value)
0 0 1 0 output on GRA compare match
0 1 0 1 output on GRA compare match
0 1 1 Toggle output on GRA compare match
(1 output on channel 2 only)
1 0 0 GRA is input Input capture to GRA on rising edge
101
capture register
Input capture to GRA on falling edge
11* Input capture on both rising and falling
edges
Note: *0 or 1
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