Hitachi SH7032 - Contention between GR Write and Compare Match

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10.6.4 Contention between GR Write and Compare Match
If a compare match occurs in the T3 state of a general register (GR) write cycle, writing takes
priority and the compare match signal is inhibited. The timing is shown in figure 10.61.
T1T2 T3
GR write cycle
GR address
N N + 1
NM
GR write data
Inhibited
CK
Address
Internal
write signal
TCNT
GR
Compare
match signal
Figure 10.61 Contention between General Register Write and Compare Match