Hitachi SH7032 - Wait State Control Register 1 (WCR1) BSC

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A.2.41 Wait State Control Register 1 (WCR1) BSC
• Start Address: H'5FFFFA2
• Bus Width: 8/16/32
Register Overview:
Bit: 15 14 13 12 11 10 9 8
Bit name: RW7 RW6 RW5 RW4 RW3 RW2 RW1 RW0
Initial value: 1 1 1 1 1 1 1 1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7 6 5 4 3 2 1 0
Bit name: — — — — — — WW1 —
Initial value: 1 1 1 1 1 1 1 1
R/W: — — — — — — R/W
*
—
Note: *Only write 0 in the WW1 bit when area 1 is DRAM space. When it is external memory
space, do not write 0.
Table A.42 WCR Bit Functions
Number of read cycles
WAIT
External Space Internal Space
Bit Bit Name Value
Pin
Signal
Input
External
Memory Space
DRAM
Space
Multi-
plex
I/O
On-Chip
Modules
On-Chip
ROM,
RAM
15–8 Read wait
state control
(RW7–RW0)
0 Not
sampled
during
read
cycle
• Areas 1, 3–5, 7:
fixed at 1 cycle
• Areas 0, 2, 6:
1 cycle + long
wait state
Column
address
cycle: Fixed
at 1 cycle
(short-pitch)
Wait
state
is 4
cycles
plus
WAIT
Fixed at
3 cycles
Fixed at 1
cycle
1 Sampled
during
read
cycle
(Initial
value)
• Areas 1, 3–5, 7:
wait state is 2
cycles plus
WAIT
• Areas 0, 2, 6:
1 cycle + long
wait state, or
wait state from
WAIT
Column
address
cycle: Wait
state is 2
cycles plus
WAIT (long-
pitch)
*