Hitachi SH7032 - General Registers A0-4 (GRA0-GRA4) ITU

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A.2.19 General Registers A0–4 (GRA0–GRA4) ITU
• Start Address: H'5FFFF0A (channel 0), H'5FFFF14 (channel 1), H'5FFFF1E (channel 2),
H'5FFFF28 (channel 3), H'5FFFF38 (channel 4)
• Bus Width: 8/16/32
Register Overview:
Bit: 15 14 13 12 11 10 9 8
Bit name:
Initial value: 1 1 1 1 1 1 1 1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7 6 5 4 3 2 1 0
Bit name:
Initial value: 1 1 1 1 1 1 1 1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Table A.20 GRA0–GRA4 Bit Functions
Bit Bit name Description
15–0 Registers used for both output
compare and input capture
Output compare register: Set with compare match
output
Input capture register: Stores the TCNT value when the
input capture signal is generated