Hitachi SH7032 - Example of DMA Transfer between On-Chip A;D Converter and External Memory

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9.4.3 Example of DMA Transfer Between On-Chip A/D Converter and External
Memory
In this example, the results of an A/D conversion by the on-chip A/D converter are transferred to
external memory using DMAC channel 3. Input from channel 0 (AN0) is A/D-converted using
scan mode. Table 9.9 shows the transfer conditions and register settings.
Table 9.9 Transfer Conditions and Register Settings for Transfer Between On-Chip A/D
Converter and External Memory
Transfer Conditions Register Setting
Transfer source: ADDRA of on-chip A/D converter SAR3 H'FFFFEE0
(ADDRAH register
address)
Transfer destination: external memory DAR3 Destination address
Number of transfers: 16 TCR3 H'0010
Transfer destination address: incremented CHCR3 H'4D0D
Transfer source address: fixed
Transfer request source (transfer request signal): A/D
converter (ADI)
Bus mode: cycle-steal
Transfer unit: word
DEI interrupt request generated at end of transfer (channel 3
enabled for transfer)
Channel priority order: fixed (0 > 3 > 2 > 1) (all channels
enabled for transfer)
DMAOR H'0001