Hitachi SH7032 - Notes and Precautions; Contention between TCNT Write and Clear

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10.6 Notes and Precautions
This section describes contention and other matters requiring special attention during ITU
operation.
10.6.1 Contention between TCNT Write and Clear
If a counter clear signal occurs in the T3 state of a TCNT write cycle, clearing the counter takes
priority and the write is not performed. The timing is shown in figure 10.58.
T1
T3T2
CK
Address
Internal write signal
Counter clear signal
TCNT
TCNT write cycle by CPU
TCNT address
N H' 0000
Figure 10.58 Contention between TCNT Write and Clear