Hitachi SH7032 - TPC Output Mode Register (TPMR)

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11.2.8 TPC Output Mode Register (TPMR)
TPMR is an eight-bit read/write register that selects between the TPC’s ordinary output and non-
overlap output modes in group units. During non-overlap operation, the output waveform cycle is
set in ITU general register B (GRB) for use as the output trigger and a non-overlap period is set in
general register A (GRA). The output value then changes on compare matches A and B. For
details, see section 11.3.4, TPC Output Non-Overlap Operation. TPMR is initialized to H'F0 by a
reset. It is not initialized in standby mode.
Bit: 7 6 5 4 3 2 1 0
Bit name: — — — — G3NOV G2NOV G1NOV G0NOV
Initial value: 1 1 1 1 0 0 0 0
R/W: — — — — R/W R/W R/W R/W
• Bits 7–4 (Reserved): These bits are always read as 1. The write value should always be 1.
• Bit 3 (Group 3 Non-Overlap Mode (G3NOV)): G3NOV selects ordinary or non-overlap mode
for TPC output group 3 (TP15–TP12).
Bit 3: G3NOV Description
0 TPC output group 3 operates normally (output value updated
according to compare match A of the ITU channel selected by TPCR)
(Initial value)
1 TPC output group 3 operates in non-overlap mode (1 output and 0
output can be performed independently according to compare match
A and B of the ITU channel selected by TPCR)
• Bit 2 (Group 2 Non-Overlap Mode (G2NOV)): G2NOV selects ordinary or non-overlap mode
for TPC output group 2 (TP11–TP8).
Bit 2: G2NOV Description
0 TPC output group 2 operates normally (output value updated
according to compare match A of the ITU channel selected by TPCR)
(Initial value)
1 TPC output group 2 operates in non-overlap mode (1 output and 0
output can be performed independently according to compare match
A and B of the ITU channel selected by TPCR)