104
8.1.4 Register Configuration
The BSC has ten registers (listed in table 8.2) which control space division, wait states, DRAM
interface, and parity check.
Table 8.2 Register Configuration
Name Abbr. R/W Initial Value Address
*
1
Bus width
Bus control register BCR R/W H'0000 H'5FFFFA0 8,16,32
Wait state control register 1 WCR1 R/W H'FFFF H'5FFFFA2 8,16,32
Wait state control register 2 WCR2 R/W H'FFFF H'5FFFFA4 8,16,32
Wait state control register 3 WCR3 R/W H'F800 H'5FFFFA6 8,16,32
DRAM area control register DCR R/W H'0000 H'5FFFFA8 8,16,32
Parity control register PCR R/W H'0000 H'5FFFFAA 8,16,32
Refresh control register RCR R/W H'0000 H'5FFFFAC 8,16,32
*
2
Refresh timer control/status
register
RTCSR R/W H'0000 H'5FFFFAE 8,16,32
*
2
Refresh timer counter RTCNT R/W H'0000 H'5FFFFB0 8,16,32
*
2
Refresh time constant
register
RTCOR R/W H'00FF H'5FFFFB2 8,16,32
*
2
Notes: *1 Only the values of bits A27–A24 and A8–A0 are valid; bits A23–A9 are ignored. For
details on the register addresses, see section 8.3.5, Area Descriptions.
*2 Write only with word transfer instructions. See section 8.2.11, Notes on Register
Access, for details on writing.
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