233
• Bit 1 (Timer Synchro 1 (SYNC1)): SYNC1 selects synchronizing mode for channel 1.
Bit 1: SYNC1 Description
0 The timer counter for channel 1 (TCNT1) operates independently
(Preset/clear of TCNT1 is independent of other channels) (Initial value)
1 Channel 1 operates synchronously. Synchronized preset/clear of
TNCT1 enabled.
• Bit 0 (Timer Synchro 0 (SYNC0)): SYNC0 selects synchronizing mode for channel 0.
Bit 0: SYNC0 Description
0 The timer counter for channel 0 (TCNT0) operates independently
(Preset/clear of TCNT0 is independent of other channels)
(Initial value)
1 Channel 0 operates synchronously. Synchronized preset/clear of
TNCT0 enabled.
10.2.3 Timer Mode Register (TMDR)
The timer mode register (TMDR) is an eight-bit read/write register that selects PWM mode for
channels 0–4, sets phase counting mode for channel 2, and sets the conditions for the overflow
flag (OVF). TMDR is initialized to H'80 or H'00 by a reset and in standby mode.
Bit: 7 6 5 4 3 2 1 0
Bit name: — MDF FDIR PWM4 PWM3 PWM2 PWM1 PWM0
Initial value: * 0000000
R/W: — R/W R/W R/W R/W R/W R/W R/W
Note: * Undefined
• Bit 7 (Reserved): Bit 7 is read as undefined. The write value should be 0 or 1.
• Bit 6 (Phase Counting Mode (MDF)): MDF selects phase counting mode for channel 2.
Bit 6: MDF Description
0 Channel 2 operates normally (Initial value)
1 Channel 2 operates in phase counting mode
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