Hitachi SH7032 - Block Diagram

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• Four types of interrupts: Transmit-data-empty, transmit-end, receive-data-full, and receive-
error interrupts are requested independently. The transmit-data-empty and receive-data-full
interrupts can start the direct memory access controller (DMAC) to transfer data.
13.1.2 Block Diagram
Figure 13.1 shows a block diagram of the SCI.
Parity
generation
Parity check
Transmit/
receive control
Baud rate 
generator
Clock
External clock
Bus interface
Internal

data bus
RxD
RDR TDR
RSR TSR
SSR
SCR
SMR
BRR
φ
φ/4
φ/16
φ/64
TEI
TXI
RXI
ERI
SCK
TxD
SCI
Module data bus
RSR: Receive shift register SMR: Serial mode register
RDR: Receive data register SCR: Serial control register
TSR: Transmit shift register SSR: Serial status register
TDR: Transmit data register BRR: Bit rate register
Figure 13.1 Block Diagram of SCI