639
A.2.68 Next Data Register A (NDRA) TPC
(When the Output Triggers of TPC Output Groups 0 and 1 are the Same)
• Start Address: H'5FFFFF5
• Bus Width: 8/16
Register Overview:
Bit: 7 6 5 4 3 2 1 0
Bit name: NDR7 NDR6 NDR5 NDR4 NDR3 NDR2 NDR1 NDR0
Initial value: 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Table A.69 NDRA Bit Functions
Bit Bit Name Description
7–4 Next data 7–4 (NDR7–
NDR4)
Stores the next output data for TPC output group 1
3–0 Next data 3–0 (NDR3–
NDR0)
Stores the next output data for TPC output group 0
A.2.69 Next Data Register A (NDRA) TPC
(When the Output Triggers of TPC Output Groups 0 and 1 are the Same)
• Start Address: H'5FFFFF7
• Bus Width: 8/16
Register Overview:
Bit: 7 6 5 4 3 2 1 0
Bit name: — — — — — — — —
Initial value: 1 1 1 1 1 1 1 1
R/W: — — — — — — — —
Table A.70 NDRA Bit Functions
Bit Bit Name Description
7–0 Reserved bits Writing is invalid; always read as 1