Hitachi SH7032 - Block Diagram; Pin Configuration

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12.1.2 Block Diagram
Figure 12.1 shows a block diagram of the WDT.
φ/2
φ/64
φ/128
φ/256
φ/512
φ/1024
φ/4096
φ/8192
Internal
clock sources
Clock
Overflow
Clock
select
Interrupt
control
Reset
control
RSTCSR TCNT TCSR
Module bus
Bus
interface
Internal data bus
ITI
(interrupt
signal)
WDTOVF
Internal
reset signal
*
WDT
TCSR: Timer control/status register
TCNT: Timer counter
RSTCSR: Reset control/status register
Note: * The internal reset signal can be generated by a register setting. The type of reset can be
selected (power-on or manual reset).
Figure 12.1 Block Diagram of WDT
12.1.3 Pin Configuration
Table 12.1 shows the pin configuration.
Table 12.1 Pin Configuration
Pin Abbreviation I/O Function
Watchdog timer overflow WDTOVF O Outputs the counter overflow signal in
watchdog mode