Hitachi SH7032 - Register Descriptions; Break Address Registers (BAR)

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6.2 Register Descriptions
6.2.1 Break Address Registers (BAR)
There are two break address registers—break address register H (BARH) and break address
register L (BARL)—that together form a single group. Both are 16-bit read/write registers. BARH
stores the upper bits (bits 31–16) of the address of the break condition. BARL stores the lower bits
(bits 15–0) of the address of the break condition. A reset initializes both BARH and BARL to
H'0000. They are not initialized in standby mode.
BARH: Break address register H.
Bit: 15 14 13 12 11 10 9 8
Bit name: BA31 BA30 BA29 BA28 BA27 BA26 BA25 BA24
Initial value: 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7 6 5 4 3 2 1 0
Bit name: BA23 BA22 BA21 BA20 BA19 BA18 BA17 BA16
Initial value: 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
• BARH Bits 15–0 (Break Address 31–16 (BA31–BA16)): BA31–BA16 store the upper bit
values (bits 31–16) of the address of the break condition.
BARL: Break address register L.
Bit:
15 14 13 12 11 10 9 8
Bit name:
BA15 BA14 BA13 BA12 BA11 BA10 BA9 BA8
Initial value:
00000000
R/W:
R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7 6 5 4 3 2 1 0
Bit name: BA7 BA6 BA5 BA4 BA3 BA2 BA1 BA0
Initial value: 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
• BARL Bits 15–0 (Break Address 15–0 (BA15–BA0)): BA15–BA0 store the lower bit values
(bits 15–0) of the address of the break condition.