Hitachi SH7032 - Usage Notes; Usage Notes on Manual Reset

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Note that delay of the BACK signal increases in units of approximately 0.1 ns/pF. (When a
capacitance of 220 pF is added, the delay increases by approximately 22 ns.)
BACK
SuperH
Microcomputer
C
Circuit with capacitor for eliminating spikes
c. Latching the BACK signal by using a flip-flop or triggering the flip-flop may or may not
be successful due to the narrow pulse width of the spike. Implement a circuit configuration
which will cause no problems when latching BACK or using BACK as a trigger signal.
When splitting the BACK signal into two signals and latching each of them using a flip-
flop or triggering the flip-flop, the flip-flop may operate for one signal but not for the other.
To capture the BACK signal using a flip-flop, receive the BACK signal using a single flip-
flop then distribute the signal (see figure below).
BACK
DQ
Q
DQ
Q
BACK
DQ
Q
Trigger OK
Trigger NG

8.11 Usage Notes
8.11.1 Usage Notes on Manual Reset
Condition: When DRAM (long-pitch mode) is used and a manual reset is performed.
The low width of RAS output may be shorter than usual in a reset (2.5 tcyc → 1.5 tcyc),
preventing the specified value (t
RAS
) of DRAM from being satisfied.