Hitachi SH7032 - Receive Data Register (RDR) SCI

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Table A.11 SSR Bit Functions (cont)
Bit Bit name Value Description
2 Transmit end
(TEND)
0 Indicates that transmission is in progress
Clear Conditions: (1) 0 written in TDRE after reading TDRE = 1;
(2) Data written to TDR by DMAC
1 Indicates that transmission has ended (Initial value)
Set Conditions: (1) Reset or standby mode; (2) TE bit in SCR is 0;
(3) TDRE = 1 when the final bit of a 1-byte serial transmit character
is transmitted
1 Multiprocessor
bit (MPB)
0 Indicates that data with multiprocessor bit = 0 has been received
(Initial value)
1 Indicates that data with multiprocessor bit = 1 has been received
0 Multiprocessor 0 0 transmitted as the multiprocessor bit (Initial value)
bit transfer
(MPBT)
1 1 transmitted as the multiprocessor bit
A.2.6 Receive Data Register (RDR) SCI
• Start Address: H'5FFFEC5 (channel 0), H'5FFFECD (channel 1)
• Bus Width: 8/16
Register Overview:
Bit: 7 6 5 4 3 2 1 0
Bit name:
Initial value: 0 0 0 0 0 0 0 0
R/W: R R R R R R R R
Bit Bit name Description
7–0 (Receive serial data storage) Store the serial data received