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Table 1.1 Features of the SH7032 and SH7034 Microcomputers (cont)
Feature Description
Direct memory
access
controller (DMAC)
(4 channels)
Permits DMA transfer between the following modules:
• External memory
• External I/O
• On-chip memory
• Peripheral on-chip modules (except DMAC)
DMA transfer can be requested from external pins, on-chip SCI, on-chip
timers, and on-chip A/D converter
Cycle-steal mode or burst mode
Channel priority level is selectable
Channels 0 and 1: dual or single address transfer mode is selectable;
external request sources are supported; channels 2 and 3: dual address
transfer mode, internal request sources only
16-bit integrated Ten types of waveforms can be output
t i mer pulse unit (ITU)
Input pulse width and cycle can be measured
PWM mode: pulse output with 0–100% duty cycle (maximum resolution:
50 ns)
Complementary PWM mode: can output a maximum of three pairs of non-
overlapping PWM waveforms
Phase counting mode: can count up or down according to the phase of an
external two-phase clock
Timing pattern Maximum 16-bit output (4 bits × 4 channels) can be output
controller (TPC)
Non-overlap intervals can be established between pairs of waveforms
Timing-source timer is selectable
Watchdog timer Can be used as watchdog timer or interval timer
(WDT) (1 channel)
Timer overflow can generate an internal reset, external signal, or interrupt
Power-on reset or manual reset can be selected as the internal reset
Asynchronous or synchronous mode is selectable
Can transmit and receive simultaneously (full duplex)
On-chip baud rate generator in each channel
Multiprocessor communication function
A/D converter Ten bits × 8 channels
Can be externally triggered
Variable reference voltage
Serial communication
interface (SCI)
(2 channels)
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