Hitachi SH7032 - Maximum Number of States from BREQ Input to Bus Release; Usage Notes on Parity Data Pins DPH and DPL

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8.11.2 Usage Notes on Parity Data Pins DPH and DPL
The following specifies the setup time, t
DS
, of parity data DPH and DPL with respect to the fall of
the CAS signal when parity data DPH and DPL are written to DRAM in long-pitch mode (early
write).
Table 8.13 Setup Time of Parity Data DPH and DPL
Item Symbol Min
Data setup time with respect to CAS
(for only DPH and DPL in long-pitch mode)
t
DS
-5ns
Therefore, when writing parity data DPH and DPL to the DRAM in long-pitch mode, delay the
WRH and WRL signals of this chip and used delayed writing. Normal data is also delay-written,
but this is not a problem.
RAS
CAS
RD
WE
CK
DQ
Q
RAS
CAS
DRAM
WRH or WRL
DWRH or DWRL
*2
*1*1
OE
SuperH
Micro-
computer
Notes: *1 To prevent signal racing
*2 Negative edge latch
Figure 8.42 Delayed-Write Control Circuit
8.11.3 Maximum Number of States from BREQ Input to Bus Release
The maximum number of states from BREQ input to bus release is:
Maximum number of states for which bus is not released + approx. 4.5 states
Note: Breakdown of approx. 4.5 states:
1.5 states: Until BACK output after end of bus cycle
1 state (min.): tBACD1
1 state (max.): tBRQS
1 state: Sampling in 1 state before end of bus cycle
BREQ is sampled one state before the bus cycle. If BREQ is input without satisfying tBRQS, the
bus is released after executing cycle B following the end of bus cycle A, as shown in figure 8.43.