Hitachi SH7032 - Serial Status Register (SSR) SCI; Transmit Data Register (TDR) SCI

568
A.2.4 Transmit Data Register (TDR) SCI
• Start Address: H'5FFFEC3 (channel 0), H'5FFFECB (channel 1)
• Bus Width: 8/16
Register Overview:
Bit: 7 6 5 4 3 2 1 0
Bit name:
Initial value: 1 1 1 1 1 1 1 1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Table A.6 TDR Bit Functions
Bit Bit name Description
7–0 (Transmit data storage) Store data for serial transmission
A.2.5 Serial Status Register (SSR) SCI
• Start Address: H'5FFFEC4 (channel 0), H'5FFFECC (channel 1)
• Bus Width: 8/16
Register Overview:
Bit: 7 6 5 4 3 2 1 0
Bit name: TDRE RDRF ORER FER PER TEND MPB MPBT
Initial value: 1 0 0 0 0 1 0 0
R/W: R/(W)
*
R/(W)
*
R/(W)
*
R/(W)
*
R/(W)
*
R R R/W
Note: *Only 0 can be written, to clear the flags.