Hitachi SH7032 - Timer Status Registers 0-4 (TSR0-TSR4) ITU

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A.2.17 Timer Status Registers 0–4 (TSR0–TSR4) ITU
• Start Address: H'5FFFF07 (channel 0), H'5FFFF11 (channel 1), H'5FFFF1B (channel 2),
H'5FFFF25 (channel 3), H'5FFFF35 (channel 4),
• Bus Width: 8
Register Overview:
Bit: 7 6 5 4 3 2 1 0
Bit name: — — — — — OVF IMFB IMFA
Initial value:
*
1
1111000
R/W: — — — — — R/(W)
*
2
R/(W)
*
2
R/(W)
*
2
Notes: *1 Undetermined
*2 Only 0 can be written, to clear the flag.
Table A.18 TSR0–TSR4 Bit Functions
Bit Bit name Value Description
2 Overflow flag (OVF) 0 Clear conditions: 0 is written in OVF after
reading OVF = 1 (Initial value)
1 Set conditions: TCNT value overflows (H'FFFF
→ H'0000) or underflows (H'FFFF → H'0000)
1 Input capture/compare match
flag B (IMFB)
0 Clear conditions: 0 is written in IMFB after
reading IMFB = 1 (Initial value)
1 Set conditions: (1) When GRB is functioning as
the output compare register, and TCNT = GRB;
(2) When GRB is functioning as the input
capture register, and the TCNT value is
transferred to GRB by the input capture signal
0 Input capture/compare match
flag A (IMFA)
0 Clear conditions: 0 is written in IMFA after
reading IMFA = 1 (Initial value)
1 Set conditions: (1) When GRA is functioning as
the output compare register, and TCNT = GRA;
(2) When GRA is functioning as the input
capture register, and the TCNT value is
transferred to GRA by the input capture signal