160
A high-level duty of 35% or 50% can be selected for the RD signal using the RD duty bit
(RDDTY) in BCR. When RDDTY is 1, the high-level duty is 35% of the T3 or T
w
state,
lengthening the access time for external devices.
8.6.2 Wait State Control
When the address/data multiplexed I/O space is accessed, the WAIT pin input signal is sampled
and a wait state inserted whenever a low level is detected, regardless of the WCR setting. Figure
8.33 shows an example in which a WAIT signal causes one wait state to be inserted.
T1
CK
A21–A0
CS
AH
Address
AD15–AD0
Address Data (output)
RD
Read
AD15–AD0
WRH, WRL
Write
T2
Tw
(wait state)
T3 T4
WAIT
Data (input)
Figure 8.33 Wait State Timing For Address/Data Multiplexed I/O Space Access
8.6.3 Byte Access Control
The byte access control signals when the address/data multiplexed I/O space is being accessed are
of two types (WRH, WRL, A0, or WR, HBS, LBS), just as for byte access control of external
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