Hitachi SH7032 - Bus Timing

477
(3) Bus Timing
Tables 20.6 to 20.8 show the bus timing.
Table 20.6 Bus Timing (1)
Conditions: V
CC
= 5.0 V ±10%, AV
CC
= 5.0 V ±10%, AV
CC
= V
CC
±10%, AV
ref
= 4.5 V to
AV
CC
, V
SS
= AV
SS
= 0 V, φ = 20 MHz, Ta = –20 to +75°C
*
Note: * Regular-specification products; for wide-temperature-range products, Ta = –40 to +85°C
Item Symbol Min Max Unit Figures
Address delay time t
AD
—20
*
1
ns 20.8, 20.9, 20.11–20.14,
20.19, 20.20
CS delay time 1 t
CSD1
— 25 ns 20.8, 20.9, 20.20
CS delay time 2 t
CSD2
—25ns
CS delay time 3 t
CSD3
— 20 ns 20.19
CS delay time 4 t
CSD4
—20ns
Access time 1
*
6
35% duty
*
2
t
RDAC1
t
cyc
× 0.65 – 20— ns 20.8,
from read strobe
50% duty t
cyc
× 0.5 – 20 — ns
Access time 2
*
6
from read strobe
35% duty
*
2
t
RDAC2
t
cyc
× (n+1.65)
– 20
*
3
— ns 20.9, 20.10
50% duty t
cyc
× (n+1.5)
– 20
*
3
—ns
Access time 3
*
6
from read strobe
35% duty
*
2
t
RDAC3
t
cyc
× (n+0.65)
– 20
*
3
— ns 20.19
50% duty t
cyc
× (n+0.5)
– 20
*
3
—ns
Read strobe delay time t
RSD
— 20 ns 20.8, 20.9, 20.11–20.15,
20.19
Read data setup time t
RDS
15 — ns 20.8, 20.9, 20.11–20.14,
Read data hold time t
RDH
0—ns
20.19
Write strobe delay time 1 t
WSD1
— 20 ns 20.9, 20.13, 20.14,
20.19, 20.20
Write strobe delay time 2 t
WSD2
— 20 ns 20.9, 20.13, 20.14,
20.19
Write strobe delay time 3 t
WSD3
— 20 ns 20.11, 20.12
Write strobe delay time 4 t
WSD4
— 20 ns 20.11, 20.12, 20.20
Write data delay time 1 t
WDD1
— 35 ns 20.9, 20.13, 20.14, 19
Write data delay time 2 t
WDD2
— 20 ns 20.11, 20.12