Hitachi SH7032 - Timer Mode Register (TMDR) ITU

576
A.2.12 Timer Mode Register (TMDR) ITU
• Start Address: H'5FFFF02
• Bus Width: 8
Register Overview:
Bit: 7 6 5 4 3 2 1 0
Bit name: — MDF FDIR PWM4 PWM3 PWM2 PWM1 PWM0
Initial value: * 0000000
R/W: — R/W R/W R/W R/W R/W R/W R/W
Note: *Undetermined
Table A.13 TMDR Bit Functions
Bit Bit name Value Description
6 Phase counting mode (MDF) 0 Channel 2 operates normally (Initial value)
1 Channel 2 in phase count mode
5 Flag direction (FDIR) 0 OVF of TSR2 set to 1 when TCNT2 overflows or
underflows (Initial value)
1 OVF in TSR2 set to 1 when TCNT2 overflows
4 PWM mode 4 (PWM4) 0 Channel 4 operates normally (Initial value)
1 Channel 4 in PWM mode
3 PWM mode 3 (PWM3) 0 Channel 3 operates normally (Initial value)
1 Channel 3 in PWM mode
2 PWM mode 2 (PWM2) 0 Channel 2 operates normally (Initial value)
1 Channel 2 in PWM mode
1 PWM mode 1 (PWM1) 0 Channel 1 operates normally (Initial value)
1 Channel 1 in PWM mode
0 PWM mode 0 (PWM0) 0 Channel 0 operates normally (Initial value)
1 Channel 0 in PWM mode