Hitachi SH7032 - Timer Interrupt Enable Registers 0-4 (TIER0-TIER4) ITU

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A.2.16 Timer Interrupt Enable Registers 0–4 (TIER0–TIER4) ITU
• Start Address: H'5FFFF06 (channel 0), H'5FFFF10 (channel 1), H'5FFFF1A (channel 2),
H'5FFFF24 (channel 3), H'5FFFF34 (channel 4),
• Bus Width: 8
Register Overview:
Bit: 7 6 5 4 3 2 1 0
Bit name: — — — — — OVIE IMIEB IMIEA
Initial value: * 1111000
R/W: — — — — — R/W R/W R/W
Note: *Undetermined
Table A.17 TIER0–TIER4 Bit Functions
Bit Bit name Value Description
2 Overflow interrupt enable (OVIE) 0 Interrupt request by OVF (OVI) disabled
(Initial value)
1 Interrupt request by OVF (OVI) enabled
1 Input capture/compare match
interrupt enable B (IMIEB)
0 Interrupt request by IMFB (IMIB) disabled
(Initial value)
1 Interrupt request by IMFB (IMIB) enabled
0 Input capture/compare match
interrupt enable A (IMIEA)
0 Interrupt request by IMFA (IMIA) disabled
(Initial value)
1 Interrupt request by IMFA (IMIA) enabled