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13.2.5 Serial Mode Register
The serial mode register (SMR) is an eight-bit register that specifies the SCI serial communication
format and selects the clock source for the baud rate generator.
The CPU can always read and write to SMR. SMR is initialized to H'00 by a reset and in standby
mode.
Bit: 7 6 5 4 3 2 1 0
Bit name: C/A CHR PE O/E STOP MP CKS1 CKS0
Initial value: 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
• Bit 7 (Communication Mode (C/A)): C/A selects whether the SCI operates in asynchronous or
synchronous mode.
Bit 7: C/A Description
0 Asynchronous mode (Initial value)
1 Synchronous mode
• Bit 6 (Character Length (CHR)): CHR selects seven-bit or eight-bit data in asynchronous
mode. In synchronous mode, the data length is always eight bits, regardless of the CHR setting.
Bit 6: CHR Description
0 Eight-bit data (Initial value)
1 Seven-bit data. When seven-bit data is selected, the MSB (bit 7) of the
transmit data register is not transmitted.
• Bit 5 (Parity Enable (PE)): PE selects whether to add a parity bit to transmit data and check the
parity of receive data, in asynchronous mode. In synchronous mode, a parity bit is neither
added nor checked, regardless of the PE setting.
Bit 5: PE Description
0 Parity bit not added or checked (Initial value)
1 Parity bit added and checked. When PE is set to 1, an even or odd
parity bit is added to transmit data, depending on the parity mode (O/E)
setting. Receive data parity is checked according to the even/odd (O/E)
mode setting.
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