Hitachi SH7032 - DMA Transfer Count Registers 0-3 (TCR0-TCR3) DMAC

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A.2.26 DMA Transfer Count Registers 0–3 (TCR0–TCR3) DMAC
• Start Address: H'5FFFF4A (channel 0), H'5FFFF5A (channel 1), H'5FFFF6A (channel 2),
H'5FFFF7A (channel 3)
• Bus Width: 16/32
Register Overview:
Bit: 15 14 13 12 11 10 9 8
Bit name:
Initial value: ********
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7 6 5 4 3 2 1 0
Bit name:
Initial value: ********
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Note: *Undetermined
Table A.27 TCR0–TCR3 Bit Functions
Bit Bit name Description
15–0 (Specifies number of DMA
transfers)
Specifies the number of DMA transfers (bytes or
words). During DMA transfer, indicates the number of
transfers remaining.