Hitachi SH7032 - DMA Operation Register (DMAOR)

186
Bit 0: DE Description
0 DMA transfer disabled (Initial value)
1 DMA transfer enabled
9.2.5 DMA Operation Register (DMAOR)
The DMA operation register (DMAOR) is a 16-bit read/write register that controls the DMA
transfer mode. It also indicates the DMA transfer status. It is initialized to H'0000 by a reset and in
standby mode.
Bit: 15 14 13 12 11 10 9 8
Bit name: —— — — — — — PR1 PR0
Initial value: 0 0 0 0 0 0 0 0
R/W: R R R R R R R/W R/W
Bit: 7 6 5 4 3 2 1 0
Bit name: — — — — — AE NMIF DME
Initial value: 0 0 0 0 0 0 0 0
R/W: R R R R R R/(W)
*
R/(W)
*
R/W
Note: * Write only 0 to clear the flag.
• Bits 15–10 (Reserved): These bits are always read as 0. The write value should always be 0.
• Bits 9 and 8 (Priority Mode Bits 1 and 0 (PR1 and PR0)): PR1 and PR0 select the priority level
between channels when there are simultaneous transfer requests for multiple channels.
Bit 9: PR1 Bit 8: PR0 Description
0 0 Fixed priority order (Ch. 0 > Ch. 3 > Ch. 2 > Ch. 1) (Initial value)
0 1 Fixed priority order (Ch. 1 > Ch. 3 > Ch. 2 > Ch. 0)
1 0 Round-robin mode priority order (the priority order immediately
after a reset is Ch. 0 > Ch. 3 > Ch. 2 > Ch. 1)
1 1 External-pin round-robin mode priority order (the priority order
immediately after a reset is Ch. 3 > Ch. 2 > Ch. 1 > Ch. 0)
• Bits 7–3 (Reserved): These bits are always read as 0. The write value should always be 0.