638
A.2.66 Next Data Enable Register A (NDERA) TPC
• Start Address: H'5FFFFF3
• Bus Width: 8/16
Register Overview:
Bit: 7 6 5 4 3 2 1 0
Bit name: NDER7 NDER6 NDER5 NDER4 NDER3 NDER2 NDER1 NDER0
Initial value: 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Table A.67 NDERA Bit Functions
Bit Bit Name Value Description
7–0 Next data enable 7–0
(NDER7–NDER0)
0 Disable TPC output TP7–TP0 disabled (Initial value)
(Transfer from NDR7–NDR0 to PB7–PB0 disabled)
1 TPC output TP7–TP0 enabled
(Transfer from NDR7–NDR0 to PB7–PB0 enabled)
A.2.67 Next Data Enable Register B (NDERB) TPC
• Start Address: H'5FFFFF2
• Bus Width: 8/16
Register Overview:
Bit: 7 6 5 4 3 2 1 0
Bit name: NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8
Initial value: 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Table A.68 NDERB Bit Functions
Bit Bit Name Value Description
7–0 Next data enable 7–0
(NDER15–NDER8)
0 TPC output TP15–TP8 disabled (Initial value)
(Transfer from NDR15–NDR8 to PB15–PB8 disabled)
1 TPC output TP15–TP8 enabled
(Transfer from NDR15–NDR8 to PB15–PB8 enabled)