Hitachi SH7032 - Stack Status after Exception Handling

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4.7 Stack Status after Exception Handling
Table 4.10 shows the stack after exception handling.
Table 4.10 Stack after Exception Handling
Type Stack Status Type Stack Status
Address
error
Upper 16 bits
Lower 16 bits
Upper 16 bits
Lower 16 bits
SR
Address of 
instruction
after instruc-
tion that has 
finished 
executing
SP
Interrupt
Upper 16 bits
Lower 16 bits
Upper 16 bits
Lower 16 bits
SR
Address of
instruction
after instruc-
tion that
has finished
executing
SP
Trap
instruc-
tion
Upper 16 bits
Lower 16 bits
Upper 16 bits
Lower 16 bits
SR
Address of
instruction
after TRAPA
instruction
SP
Illegal
slot
instruc-
tion
Upper 16 bits
Lower 16 bits
Upper 16 bits
Lower 16 bits
SR
Branch
destination
address of
delayed
branch
instuction
SP
General
illegal
instruc-
tion
Upper 16 bits
Lower 16 bits
Upper 16 bits
Lower 16 bits
SR
Start add-
ress of 
illegal
instruction
SP
Note: Stack status is based on a bus width of 16 bits.