Hitachi SH7032 - Interrupts; Timing of Setting Status Flags

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10.5 Interrupts
The ITU has two interrupt sources: input capture/compare match and overflow.
10.5.1 Timing of Setting Status Flags
Timing for Setting IMFA and IMFB in a Compare Match: The IMF bits in TSR are set to 1 by
a compare match signal generated when TCNT matches a general register. The compare match
signal is generated in the last state in which the values match (when TCNT is updated from the
matching count to the next count). Therefore, when TCNT matches GRA or GRB, the compare
match signal is not generated until the next timer clock input. Figure 10.54 shows the timing of
setting the IMF bits.
CK
TCNT 
input clock
TCNT
GR
Compare 
match signal
IMF
IMI
N
N
N + 1
Figure 10.54 Timing of Setting Compare Match Flags (IMFA, IMFB)