Hitachi SH7032 - Wait State Control

146
CK
A21–A0
RAS
CAS
WRH, WRL
AD15–AD0
T
p
Write
WRH, WRL
AD15–AD0
Read
T
r
T
c
1
Row address Column address
T
c
2
Figure 8.18 Long Pitch Access Timing
8.5.3 Wait State Control
Precharge State Control: When the microprocessor clock frequency is raised and the cycle
period shortened, 1 cycle may not always be sufficient for the precharge time for the RAS signal
when the DRAM is accessed. The BSC allows the precharge cycle to be set to 1 state or 2 states
using the RAS signal precharge cycles bit (TPC) in DCR. When the TPC bit is 0, the precharge
cycle is 1 state; when TPC is 1, the precharge cycle is 2 states. Figure 8.19 shows the timing when
the precharge cycle is 2 states.