Hitachi SH7032 - Stack after Interrupt Exception Handling

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5.4.2 Stack after Interrupt Exception Handling
Figure 5.3 shows the stack after interrupt exception handling.
Upper 16 bits
Lower 16 bits
Upper 16 bits
Lower 16 bits
SR
PC
*1
Address
4n–8
4n–6
4n–4
4n–2
4n
SP
*2
Notes: Bus width is 16 bits.
*1 PC stores the start address of the next instruction (return instruction) after the
executed instruction.
*2 The value of SP must always be a multiple of four.
Figure 5.3 Stack after Interrupt Exception Handling