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8.1.2 Block Diagram
Figure 8.1 shows a block diagram of the bus state controller.
WCR1
WCR2
WCR3
BCR
DCR
RCR
CASH, CASL
CMI interrupt request
DPH, DPL
PEI interrupt request
WAIT
RTCSR
RTCNT
RTCOR
PCR
Internal bus
Interrupt
controller
Bus
interface
Area control
unit
Comparator
Module bus
RD
WRH, WRL
HBS, LBS
AH
CS7 to CS0
RAS
Wait control
unit
DRAM
control
unit
Parity control
unit
Peripheral bus
BSC
WCR: Wait state control register RTCSR: Refresh timer control/status register
BCR: Bus control register RTCNT: Refresh timer counter
DCR: DRAM area control register RTCOR: Refresh time constant register
RCR: Refresh control register PCR: Parity control register
Figure 8.1 Block Diagram of BSC
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