Hitachi SH7032 - Register Tables; A.2 Register Tables; Serial Mode Register (SMR) SCI

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A.2 Register Tables
A.2.1 Serial Mode Register (SMR) SCI
• Start Address: H'5FFFEC0 (channel 0), H'5FFFEC8 (channel 1)
• Bus Width: 8/16
Register Overview:
Bit: 7 6 5 4 3 2 1 0
Bit name: C/A CHR PE O/E STOP MP CKS1 CKS0
Initial value: 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Table A.3 SMR Bit Functions
Bit Bit name Value* Description
7 Communication mode (C/A) 0 Asynchronous mode (Initial value)
1 Synchronous mode
6 Character length (CHR) 0 8-bit data (Initial value)
1 7-bit data
5 Parity enable (PE) 0 Parity bit addition and check disable
(Initial value)
1 Parity bit addition and check enable
4 Parity mode (O/E) 0 Even parity (Initial value)
1 Odd parity
3 Stop bit length (STOP) 0 1 stop bit (Initial value)
1 2 stop bits
2 Multiprocessor mode (MP) 0 Multiprocessor function disabled (Initial value)
1 Multiprocessor function selected
1,0 Clock select 1, 0 (CKS1, CKS0) 0 0 φ clock (Initial value)
01φ/4 clock
10φ/16 clock
11φ/64 clock
Note: *When 2 or more bits are treated as a group, the left side is the upper bit and the right the
lower bit.