Hitachi SH7032 - Page 599

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Table A.2 16-bit Access Space (In Principle, 8-Bit, 16-Bit and 32-bit Accessible) (cont)
Bit Name
Address Register 7 6 5 4 3 2 1 0 Module
H'5FFFFD2–
H'5FFFFED
— ————————PFC
H'5FFFFEE CASCR CASH
MD1
CASH
MD0
CASL
MD1
CASL
MD0
— ———
H'5FFFFEF — — — — — — — — TPC
H'5FFFFF0 TPMR — — — — G3N
OV
G2N
OV
G1N
OV
G0N
OV
H'5FFFFF1 TPCR G3C
MS1
G3C
MS0
G2C
MS1
G2C
MS0
G1C
MS1
G1C
MS0
G0C
MS1
G0C
MS0
H'5FFFFF2 NDERB NDE
R15
NDE
R14
NDE
R13
NDE
R12
NDE
R11
NDE
R10
NDE
R9
NDE
R8
H'5FFFFF3 NDERA NDE
R7
NDE
R6
NDE
R5
NDE
R4
NDE
R3
NDE
R2
NDE
R1
NDE
R0
H'5FFFFF4 NDRB
*
4
NDR15 NDR14 NDR13 NDR12 — — — —
H'5FFFFF5 NDRA
*
4
NDR7 NDR6 NDR5 NDR4 — — — —
H'5FFFFF6 NDRB
*
4
— — — — NDR11 NDR10NDR9 NDR8
H'5FFFFF7 NDRA
*
4
— — — — NDR3 NDR2 NDR1 NDR0
H'5FFFFF8– — — — — — — — — —
H'5FFFFFF
Notes *1 Only 8-bit accessible. 16-bit and 32-bit access disabled.
*2 Register shared by all channels.
*3 Address for read. For writing, the addresses are H'5FFFFB8 for TCR and TCNT and
H'5FFFFBA for RSTCSR. For more information, see section 12, Watchdog Timer
(WDT), particularly section 12.2.4, Notes on Register Access.
*4 When the output triggers for TPC output group 0 and TPC output group 1 set by TPCR
are the same, the NDRA address is H'5FFFFF5; when the output triggers are different,
the NDRA address for group 0 is H'5FFFFF7 and the NDRA address for group 1 is
H'5FFFFF5. Likewise, when the output triggers for TPC output group 2 and TPC output
group 3 set by TPCR are the same, the NDRB address is H'5FFFFF4; when the output
triggers are different, the NDRB address for group 2 is H'5FFFFF6 and the NDRB
address for group 3 is H'5FFFFF4.
*5 16-bit and 32-bit accessible. 8-bit access disabled.