Hitachi SH7032 - Example of DMA Transfer between On-Chip SCI and External Memory

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9.4.2 Example of DMA Transfer between On-Chip SCI and External Memory
In this example, receive data of on-chip serial communication interface (SCI) channel 0 is
transferred to external memory using DMAC channel 3. Table 9.8 shows the transfer conditions
and register settings.
Table 9.8 Transfer Conditions and Register Settings for Transfer between On-Chip SCI
and External Memory
Transfer Conditions Register Setting
Transfer source: RDR0 of on-chip SCI0 SAR3 H'FFFFEC5
Transfer destination: external memory DAR3 Destination address
Number of transfers: 64 TCR3 H'0040
Transfer destination address: incremented CHCR3 H'4405
Transfer source address: fixed
Transfer request source (transfer request signal): SCI0 (RXI0)
Bus mode: cycle-steal
Transfer unit: byte
DEI interrupt request generated at end of transfer (channel 3
enabled for transfer)
Channel priority order: fixed (0 > 3 > 2 > 1) (all channels
enabled for transfer)
DMAOR H'0001